In computer architectures, the result of an execution of a given instruction causes the processor to maintain a particular state. A summary of the result of a given operation is stored as a condition code, and the state is referred to as a condition code state. Changes in program flow, such as caused by a conditional branch, are achieved by testing and branching on a particular condition code state. However, many computer systems suffer a settling delay between the setting of the condition codes to the use of those condition codes by a conditional branch instruction. In some computer systems, time is wasted by either increasing the machine's cycle time or the injection of a system stall. Either approach requires the branch instruction to wait for the condition codes to stabilize reducing system performance. Pipeline processors have instructions which are partitioned into several cycles of execution, each cycle of which is completed at different and sequential time periods, and have the cycles of the instruction partially overlapping to allow the most efficient execution of all such pipelined instructions. Pipeline processors are particularly penalized when the program flow is altered by a branch instruction. As a technique to reduce this penalty, the step of branching on condition code state by instruction (i+1) is overlapped with the step of instruction execution by the prior instruction, i. However, this action leads to a condition code settling delay of one cycle in that instruction (i+1) not alter condition code state while the condition codes becomes stable for use in instruction i+2. Condition code settling imposes the restriction that there is a single instruction delay (referred to as the later instruction) between an instruction which alters condition code state relative to an instruction which uses that updated state. This restriction restrains the compiler from assigning instructions as latency instructions. As a result, processor performance is reduced since useful latency instructions cannot be assigned.